Volatile and non-volatile memory devices have a number of applications, such as in digital cameras and measuring instruments, for example. A functional block diagram of a common memory device supporting the serial communication protocol known as the Firmware Hub protocol, and another commonly used serial communication protocol known as the low pin count type (LPC) is shown in FIG. 1.
These serial communication protocols may be supported by the same device because the protocols require compatible characteristics. That is, they may be alternately used in memory devices having the same arrangement and number of I/O pins (4). This may include, in particular, a dedicated pin for the provision of an externally generated timing signal CK_PAD, and a dedicated pin for the provision of the start signal of the preamble LFRAME.
Typically these memory devices include a standard flash memory core having a serial communication interface LPC/FWH INTERFACE coupled to four I/O pins LPC_PAD<3:0> for transferring data and addresses to a dedicated pin for receiving a clock signal CK_PAD, and to another dedicated pin LFRAME for receiving a start signal of a cycle of the communication protocol. The interface generates the internal commands Chip Enable (CE) and Write Enable (WE), respectively, to enable the standard memory core and to permit writing operations in the memory array.
The device receives through the pins connected to the external bus LPC/FWH BUS the commands relative to the various cycles of the communication protocol, addresses and data. The data received through LPC_PAD<3:0> are arranged in a parallel mode by the interface for conveying them to the standard memory core FLASH CORE through the internal address bus ADDR<20:0> and the internal data bus DBUS<15:0>.
A configuring circuit CAM SETTING generates a logic signal CAM that configures the memory device for either the Firmware Hub communication protocol or for a different LPC protocol. During a test-on-wafer or EWS phase of the fabrication process of the device, the CAM SETTING circuit is permanently configured to make the fabricated memory device capable of functioning with a Firmware Hub protocol or with a different LPC protocol. This is based on the customer's specification.
Typically, the CAM SETTING circuit contains a non-volatile memory cell, for example a FLASH EPROM, that stores a CAM bit that specifies the type of serial communication protocol that is enabled. This way of fabricating memory devices is convenient for the manufacturer because it permits the same memory device to be fabricated, which is eventually configured based upon the customer's preference during a final step of the fabrication process for the selected serial communication protocol of the two possible alternatives.
FIG. 2 shows an input buffer of the memory device of FIG. 1. An internal signal INTERNAL_SIGNAL is produced as replica of an input signal available on any one of the input pins (INPUT_PIN) only if the inverted replica CE_N of the Chip Enable signal assumes the low logic state. When the signal CE_N assumes the high logic state, the node on which the INTERNAL_SIGNAL is produced is grounded (GND).
FIG. 3 shows a typical output buffer of the memory device of FIG. 1. The output buffer is substantially a pull-up_pull-down stage driven by a logic signal EN and by its inverted replica EN_N, to be replicated on an output pin of the device (OUTPUT_PIN).
FIG. 4 shows the sequence of cycles for performing a read operation according to a Firmware Hub protocol, which includes the following cycles. A Start_Code preamble signals the start of a protocol cycle and specifies whether a write operation or a read operation is requested. An Idsel_Code cycle identifies the memory device called to transfer data with the external system host. Seven Add_Code cycles communicate the address of the memory location in which the external host is to perform either a read or write operation. A Msize cycle specifies the number of bytes that is to be read, and two Tar_Code cycles by which the external host gives control of the system bus to the memory device.
After these last two cycles, the standard FLASH CORE memory engages the system bus. Thereafter, the FLASH CORE generates wait cycles Sync_Code, during which it performs internal operations. Once the reading of data has been completed, the FLASH CORE delivers the read data through the cycles Data_L and Data_H, and thereafter, by two more Tar_Code cycles, the FLASH CORE relinquishes control of the system bus to the external host.
As mentioned above, this type of memory device is permanently configured at the end of the fabricating process to utilize only a selected serial communication protocol, for example a Firmware Hub protocol or a different LPC protocol. In general, so-called LPC protocols distinguish among themselves by the sequence of cycles through which the standard memory core is accessed. These protocols have in common the fact of using a start signal supplied to the device through a dedicated pin LFRAME, and the fact that the communication of data or commands is timed by a clock signal supplied to the device through a dedicated pin CK_PAD.
On the other hand, another serial mode access protocol that is frequently utilized is the so-called SPI protocol. This protocol requires a clock pin CK_PAD, a selection pin SELECT, an input pin and an output pin. A sample sequence of the cycles of an SPI protocol is depicted in FIG. 5. The leading high-to-low transition edge of the SELECT signal starts the SPI communication protocol. During the first eight clock cycles instructions on the operations to be carried out are received and the interface recognizes whether a read or a write operation is requested. In the successive twenty-four clock cycles, addresses of the memory location to be accessed are communicated.
Thereafter, data are transmitted in n clock cycles. Finally, the trailing edge (low-to-high transition) of the SELECT signal indicates that the read or write operation is complete. Moreover, often the user must preliminary program the standard memory core of the device. In view of the fact that such a preliminary program operation implies the writing of a large quantity of data, it is more convenient to access the memory device in a parallel mode rather than in a serial mode.
For this reason memory devices have been developed to be capable of selectively functioning with a serial or with a parallel communication protocol. Normally, these devices have a dedicated pin for receiving a selection signal IC for a parallel mode of operation. When the selection signal IC is inactive, the memory devices function in a serial mode, communicating according to a SPI protocol. Otherwise, the memory devices function according to a parallel communication protocol.
Such an optionally selectable parallel communication protocol may be supported by memory devices that have at least 11 address pins, 8 I/O data pins and which use a control signal for multiplexing the addresses when functioning in a parallel access mode. The parallel functioning is automatically selected by the IC signal, and when it is active, the standard memory core is automatically enabled. Data are read from the memory by column and by rows, depending on the logic value of an address multiplexing signal RC, as depicted in FIG. 6.
A parallel communication protocol having such characteristics may be defined as an A/AMUX protocol (shortly for address/address multiplexer). Because of the different requirements of specific serial communication protocols and of parallel communication protocols, it has not been possible so far to form memory devices that could be configured at fabrication level for supporting a Firmware Hub serial communication protocol or a different LPC serial communication protocol besides an SPI serial communication protocol and a parallel communication protocol of the type A/AMUX, without significantly increasing the number of pins. However, an increase in the number of pins is often unacceptable or costly.